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COURSE UNIT TITLECOURSE UNIT CODESEMESTERTHEORY + PRACTICE (Hour)ECTS
DIGITAL LOGIC DESIGN BİL275 Third Term (Fall) 3 + 2 7

TYPE OF COURSE UNITCompulsory Course
LEVEL OF COURSE UNITBachelor's Degree
YEAR OF STUDY2
SEMESTERThird Term (Fall)
NUMBER OF ECTS CREDITS ALLOCATED7
NAME OF LECTURER(S)Instructor Oğul Göçmen
LEARNING OUTCOMES OF THE COURSE UNIT At the end of this course, the students;
1) To learn the basic concepts of digital logic and to implement to engineering applications.
2) To learn Digital logic based circuit design.
3) Acknowledgement of basic elements used in digital logic.
4) To convert real word logic problems to digital logic problems, to determine input and output variables, to design and conversion.
MODE OF DELIVERYFace to face
PRE-REQUISITES OF THE COURSENo
RECOMMENDED OPTIONAL PROGRAMME COMPONENTNone
COURSE DEFINITIONAnalog and Digital system definitions, applications, benefits, Binary Systems. Conversion among binary sistems, coding systems, Logic gates. Boolean Algebra rules. Minimization of Logic functions. Combinational Logic. Flip Flops and Synchronous Sequential Logic. Registers and Counters. Memory and Programmable Logic.
COURSE CONTENTS
WEEKTOPICS
1st Week Digital Systems, Numbers And Number Systems, Codes, Error Detection Codes
2nd Week Digital Systems, Numbers And Number Systems, Codes, Error Detection Codes
3rd Week Error Detection Codes, Boolean Algebra And Boolean Arithmetic's, Digital Logic Gates
4th Week Error Detection Codes, Boolean Algebra And Boolean Arithmetic's, Digital Logic Gates
5th Week Gate Level Minimization, Karnaugh Map, NAND/NOR Implementation, XOR/XNOR Gates
6th Week Gate Level Minimization, Karnaugh Map, NAND/NOR Implementation, XOR/XNOR Gates
7th Week Combinational Circuits, Analysis And Design, Adders and Subtractor Circuits, Binary Multipliers, Coders And Decoders.
8th Week Midterm
9th Week Synchronous Sequential Logic, Flip-Flops, Analysis And Design Of Clocked Sequential Circuits, Level Minimization
10th Week Synchronous Sequential Logic, Flip-Flops, Analysis And Design Of Clocked Sequential Circuits, Level Minimization
11th Week Registers, Shift Registers, Ripple Registers, Synchronous Registers
12th Week Registers, Shift Registers, Ripple Registers, Synchronous Registers
13th Week Memory And Usage, Read Only Memory, Programmable Logic Array
14th Week Memory And Usage, Read Only Memory, Programmable Logic Array
RECOMENDED OR REQUIRED READING1. Mano Morris, Digital Design, 3/E, ISBN: 013062121-8, Prentice Hall, 2002
2. Floyd Thomas L., Digital Fundamentals, 8/E, ISBN: 8177587633, Prentice Hall, 2002
PLANNED LEARNING ACTIVITIES AND TEACHING METHODSLecture,Questions/Answers,Experiment,Practice,Problem Solving,Report Preparation,Presentation
ASSESSMENT METHODS AND CRITERIA
 QuantityPercentage(%)
Mid-term130
Assignment15
Quiz515
Practice515
Total(%)65
Contribution of In-term Studies to Overall Grade(%)65
Contribution of Final Examination to Overall Grade(%)35
Total(%)100
ECTS WORKLOAD
Activities Number Hours Workload
Midterm exam122
Preparation for Quiz4624
Individual or group work
Preparation for Final exam14545
Course hours14570
Preparation for Midterm exam13535
Laboratory (including preparation)5525
Final exam122
Homework
Quiz414
Total Workload207
Total Workload / 306,9
ECTS Credits of the Course7
LANGUAGE OF INSTRUCTIONEnglish
WORK PLACEMENT(S)No
  

KEY LEARNING OUTCOMES (KLO) / MATRIX OF LEARNING OUTCOMES (LO)
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K2  X       X
K3    X     X
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K5    X   X   X
K6      X   X
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K12